Tektronix BSX320 Bit Error Rate Tester (BERT)
The Tektronix BSX320 Bit Error Rate Tester introduces a receiver test platform capable of supporting emerging 4th-generation standards and beyond. With the addition of powerful data processing and internal Tx equalization, the Tektronix BSX320 supports protocol-based handshaking and synchronization with your device under test (DUT). The Tektronix BSX320 includes interactive link training at data rates up to 32 Gb/s. This bit error rate tester shortens the time to debug the physical layer and link training issues. Additionally, this unit provide the quickest path to compliance for a broad range of industry standards.
The BSX320 memory sequencer implements flexible, indirect access to pattern memory. The pattern memory can support two levels of loop nesting with up to 1 million iterations per loop. To further simplify programming and increase memory efficiency, individual pattern segments can be any size greater than 128 bits. Advancement of the memory sequence can be controlled by software control, external signal, or detector pattern match -- this provides the user with multiple means of controlling handshaking with their test devices.
The BSX320 is part of the Tektronix BSX series of Bit Error Rate Testers.
| Frequency range | 1 to 32 Gb/s |
| Connector | 3.5 mm |
| Impedance | 50 Ω |
| Threshold voltage | –2 to +3.5 V |
| Threshold presets | LVPECL, LVDS, LVTTL, CML, ECL, SCFL |
| Terminations | Variable: –2 V to +3 V Presets: +1.5, +1.3, +1, 0, –2 V, AC coupled |
- Provides a single solution for receiver stress testing, debugging, and compliance.
- Test Gen-3 and Gen-4 standards including PCIe, SAS, and USB 3.1 and proprietary standards.
- DUT handshaking capability above 16 Gb/s supporting RX test requirements for loopback initiation and adaptive link training for key standards such as PCIe.
- Protocol-aware pattern generation and error detection supports flexible stimulus response programmability and debugging of handshaking issues.
- Forward error correction (FEC) emulation option supports measurement of BER both before and after error correction for commonly used Reed-Solomon FEC codes.
- Calibration and test automation software available for key standards.
- Design verification including signal integrity, jitter, and timing analysis.
- Design characterization for high-speed, sophisticated designs.
- Design/Verification of high-speed I/O components and systems including DUT handshaking.